1. Field of the Invention
This invention relates to SRAM MOSFET devices and more particularly to contacts to interconnection lines therein.
2. Description of Related Art
U.S. Pat. No. 4,581,623 of Wang for "Interlayer Contact for Use in a Static RAM Cell" shows the formation of a silicide layer between a P-type and N-type polysilicon layer.
U.S. Pat. No. 5,336,916 of Chan et al. for "SRAM Cell and Structure with Polycrystalline P-Channel Load Devices" shows a method of forming an SRAM cell with polysilicon P-channel load devices. Chan et al. forms an interconnect layer 35 formed of N type polysilicon layer 36 and a barrier layer 37 (preferably a silicide) between an N and a P type polysilicon bottom gate electrode layer 40, but in a different area from that of the present invention. N type polysilicon layer 36 is formed above the S/D region 22.
See col. 3 of U.S. Pat. No. 5,605,853 of Yoo et al. for "Method of Making a Semiconductor Device Having 4-Transistor SRAM and Floating Gate Memory Cells" which shows a conventional method of forming a contact in an SRAM cell.
See also U.S. Pat. No. 4,398,335 of Lehrer for "Multilayer Metal Silicide Interconnections for Integrated Circuits" and U.S. Pat. No. 4,800,177 of Nakamae for "Semiconductor Device Having Multilayer Silicide Contact System and Process of Fabrication Thereof."